Mahrous
Newbie level 6
i have a spartan6 -SP605- fpga board , wrote SPI slave module on it ,
the problem is the clock from the master is not always read correctly , i managed to implement a debugcore using chipscope and viewed the clock , some times it appears to be perfect other times it has some missing edges ~ most of the time i get a very noisy clock ,
i use a 3-bit vector register for synchronizing this clock , the fpga's internal clock is much faster ,
any suggestions ?. some told me to try and remove the input buffer of the clock implemented automatically by the synthesizer . does this solve the problem ? and how?
thanks in advance ,plz help .
the problem is the clock from the master is not always read correctly , i managed to implement a debugcore using chipscope and viewed the clock , some times it appears to be perfect other times it has some missing edges ~ most of the time i get a very noisy clock ,
i use a 3-bit vector register for synchronizing this clock , the fpga's internal clock is much faster ,
any suggestions ?. some told me to try and remove the input buffer of the clock implemented automatically by the synthesizer . does this solve the problem ? and how?
thanks in advance ,plz help .