unsigned char Theta1,Theta2,Theta3,Count2,Count3,datain,intiCom, ready,Thetax=0,Thetay,Thetaz,x,y,z1,reset;
unsigned char Write(char dataout);
void mapInput();
void SysInit();
void sent_data(unsigned char Theta1 ,unsigned char Theta2 , unsigned char Theta3 );
void main(){
SysInit();
intiCom=0;
PORTB=0xFF;
delay_ms(1000);
PORTB=0x00;
intiCom=Write(0x0F); // inititalize the communication: 1
//Send 0x0F if reviced is F0 the Communication line is stablish
PORTB = intiCom;
//Delay_ms(500);
if(intiCom==0xF0)
{
while(1)
{
sent_data(45,45,1);
delay_ms(500);
sent_data(45,45,2);
}
}
}
unsigned char Write(unsigned char dataout)
{
PORTD = dataout;
PORTC.B2=0; // SS select low slave is selected port C pin 2
delay_ms(50); // wait
SPI1_Write(dataout); // transmit the dataout
while(SSPSTAT.BF); // wait till end of data transmission
delay_ms(50); // wait.
PORTC.B2=1;
return SSPBUF;
}
void SysInit()
{
TRISA=0xFF; // configure Port A as input
ADCON1=0x06;// disable ADC and make all the pins of Port A as digital input.
TRISD=0x00; // configure Port D as output
PORTD=0x00; // Clear all pin of Port D
TRISB=0x00; // configure Port B as output
PORTB=0x00; // Clear all pin of Port B
TRISC.B2=0; // Output for Slave select
TRISC.B3=0; // SCK output
TRISC.B4=1; // SDI input
TRISC.B5=0; // SDO output
PORTC.B2=1; // SS select high no slave is select
//Set SPI1 module to master mode, clock = Fosc/4, data sampled at the middle of interval,
//clock idle state low and data transmitted at low to high edge:
SPI1_Init_Advanced(_SPI_MASTER_OSC_DIV4, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_LOW, _SPI_LOW_2_HIGH); // Setup the spi
}
void sent_data(unsigned char Theta1 ,unsigned char Theta2 , unsigned char Theta3 )
{
ready=Write(0x10); //2
Delay_ms(50);
if(ready==0x70)
{
Thetax=Write(Theta1); //3
Delay_ms(50);
}
if(Thetax==0x30)
{
x=Write(0x05); //4
Delay_ms(50);
}
if(x==0x40)
{
Thetay=Write(Theta2); //5
Delay_ms(50);
}
if(Thetay==0x50)
{
y=Write(0x06); //6
Delay_ms(50);
}
if(y==0x60)
{
Thetaz=Write(Theta3); //7
//PORTB=Thetaz;
Delay_ms(50);
}
if(Thetaz==0x80)
{
z1=Write(0x08); //8
//PORTB=z1;
Delay_ms(50);
}
if((z1==0x90)&&(y==0x60)&&(x==0x40))
{
reset= Write(0x09); //9
z1=0;
y=0;
x=0;
Thetaz=0;
Thetay=0;
Thetax=0;
ready=0;
PORTB=Theta3;
}
}