while(1)
{
S0SPCCR = 32; // SCLK rate
S0SPCR =
0x00000000 | // MOSI valid on raising edge of SCLK (CPOL=CPHA=0)
0x00000020 | // master (AD7390 DAC is the slave)
0x00000000 | // MSbit first
0x00000000 | // SPI interrupt inhibited
0x000C0004; // transmit 12 bits (BitEnable, BITS)
DAC_xLD_FSET = DAC_xLD_MASK; // drive LD# high
S0SPDR = 0x7FF; // write to the data register (this will start the transmission and clear the SPIF bit)
while ( !(S0SPSR & 0x80) ); // poll SPIF bit for the end of transaction
DAC_xLD_FCLR = DAC_xLD_MASK; // drive LD# low (data gets written from serial shift register to DAC register)
}