[SOLVED] SPI MOSI pin status after data transfer??

[shrikantbhairavkar]

HI I am using microcontroller STM32F103C8T6. I am utilising its SPI engine & want to interface device ET1200. Requirement for this ASIC is that MOSI pin should be always high after each data transfer.

Controller STM32F is master. I have pulled-up the MOSI & MISO pin using 4K7 resistor. But my observations are that though pulled-up the MOSI pin gets latched to last data bit transfered through SPI, So please help me how to pull-up my MOSI line high after every data transfer?????.

Please help me its urgent its my last year project.

 

[shaiko]

not familiar with STM32F MCU, but...I understand that you have the MOSI pin open drained (open collector transistor with an external pullup).

Am I correct?
If so, why did you do it? Why don't you use the IC itself to "push" the desired logic level?

 

[FvM]

Holding the last bit level for MOSI is in fact SPI standard behaviour. You can however refer to the bidirectional mode of SPI interface, that allows to tri-state MOSI after a transmission.

 

[shaiko]

But why use an open drain output?
It's not part of the protocol...

 

[FvM]

But why use an open drain output?
It's not part of the protocol...

Right. The chip doesn't provide open drain opereation. But it's an option to achieve high level output with tri-stated MOSI driver. The other option may be to reprogram the IO pins during SPI pauses.

 

[shrikantbhairavkar]

Thank you shaiko but is it so that MOSI pin gets latched to last bit of the datasent or recieved?? Plz help

 

[shaiko]

The reason for a high 'Z' on the MOSI pin is to allow it to function as an input to the IC.
That doesn't mean that you need to pull it up (or down) to a logic level.

Don't think that's what causes your problem...but I suggest you eliminate the pullup R and use a push pull configuration instead.
After you do that, make sure that you're code for the master doesn't high 'Z' the MOSI pin, and instead drives a logic high '1'.

Also, make sure that you're slave is always configured as such!
Some IC designs implement SPI cores that can function both as a master as well as a slave.
It's rather unlikely, but if your slave can do that - make sure that you aren't causing such a transition by software.

Please refer to the above document for further details:
**broken link removed**

Make sure that your SS (slave select) line functions correctly and that it isn't your code that actually "latches" the MOSI value to the last level.

 

[FvM]

After you do that, make sure that you're code for the master doesn't high 'Z' the MOSI pin, and instead drives a logic high '1'.

As previously mentioned, this is not a feature of the ARM3 SPI function. Reprogramming the IOs can work, but may be incompatible with other application requirements. Obviously, the pin isn't yet tri-stated, and I don't know what makes you think, that tri-stating will cause problems?

It's not clear to me, what causes this, but it's celarly beyond regular SPI functionality:

Requirement for this ASIC is that MOSI pin should be always high after each data transfer.

 

[shaiko]

I didn't say that it's the cause - just that it's unnecessary and isn't part of the SPI protocol.
Also, it will decrease the maximum bus speed.

 

[shrikantbhairavkar]

Dear Frendz thanks for your reply. Even I observe that only by software only I will have to set/resset mosi pin after disabling SPI.