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spectreVerilog has error (Error! Line is too long - being truncated [verilog-ltlt])

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leonel.mendoza

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spectreVerilog has error below:
Error! Line is too long - being truncated [Verilog-LTLT]
"saveDefs", 939:

Error! sysntax error [Verilog]
"textfixture.template", 36:endmodule<-

How can I fix the above errror?

Anyone can help?? Pls.
 

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