neoflash
Advanced Member level 1
Hi, folks:
I do have a trouble with simulation with Spectra_Verilog. The problem is that there is often a lot of glitches on the interface signals between analog and digital. If the signal is a clock, it will incur double trigger.
How to entirely solve this problem?
Regards
I do have a trouble with simulation with Spectra_Verilog. The problem is that there is often a lot of glitches on the interface signals between analog and digital. If the signal is a clock, it will incur double trigger.
How to entirely solve this problem?
Regards