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Spectra_Verilog simulation: Glitch on AD/DA interface

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neoflash

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Hi, folks:

I do have a trouble with simulation with Spectra_Verilog. The problem is that there is often a lot of glitches on the interface signals between analog and digital. If the signal is a clock, it will incur double trigger.

How to entirely solve this problem?

Regards
 

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