Special counter: set&reset triggered by rising edge of p

library IEEE;
use IEEE.std_logic_1164.all;

entity act_dff_sync_pre is
port (data, clk, preset	: in std_logic;
		q						: out std_logic);
end act_dff_sync_pre;

architecture behave of act_dff_sync_pre is
begin
process (clk)
begin
	if (clk'event and clk = '1') then
		if (preset = '0') then
			q <= '1';
		else
			q <= data;
		end if;
	end if;
end process;
end behave;

library IEEE;
use IEEE.std_logic_1164.all;

entity act_dff_sync_rst is
port (data, clk, reset	: in std_logic;
		q						: out std_logic);
end act_dff_sync_rst;

architecture behave of act_dff_sync_rst is
begin
process (clk)
begin
	if (clk'event and clk = '1') then
		if (reset = '0') then
			q <= '0';
		else
			q <= data;
		end if;
	 end if;
end process;
end behave;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity counter is
	port
	(
		clk, set, rst	: in std_logic;
		count			: out std_logic_vector (7 downto 0)
	);
end counter;

architecture behave of counter is
	signal	cnt:	std_logic_vector (7 downto 0);
begin
	process (clk, cnt, rst, set)
		begin
		
			if (clk'event and clk = '1') then
				if (rst = '0') then
					cnt <= (others => '0');
				elsif (set = '0') then
					cnt <= (others => '1');
				else 
					cnt <= cnt + '1';
				end if;
			end if;
	end process;
			count <= cnt;
end behave;

architecture Behavioral of fjkc is
  begin
   process (C, CLR)
     begin
     if (CLR=’1’) then
       Q <= ’0’;
     elsif (C’event and C=’1’) then
       if (J=’0’) then
         if (K=’1’) then
           Q <= ’0’;
         end if;
       else
         if (K=’0’) then
           Q <= ’1’;
         else
           Q <= not Q;
         end if;
       end if;
     end if;
   end process;
end Behavioral