Sep 19, 2006 #1 javad Member level 3 Joined Aug 18, 2004 Messages 57 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,288 Activity points 495 io pins of spartan3 Hi, How can I prevent FPGA I/O pins from going High(Active) during configuration process? Thanks.
io pins of spartan3 Hi, How can I prevent FPGA I/O pins from going High(Active) during configuration process? Thanks.
Sep 19, 2006 #2 B bis_ Member level 2 Joined Jun 21, 2006 Messages 50 Helped 14 Reputation 28 Reaction score 0 Trophy points 1,286 Activity points 1,573 io pins of spartan3 The pin HSWAP_EN is responsible for float/pull-up near all pins during configuration. bis
io pins of spartan3 The pin HSWAP_EN is responsible for float/pull-up near all pins during configuration. bis
Sep 21, 2006 #3 I issaiass Member level 3 Joined Oct 21, 2004 Messages 59 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,288 Activity points 404 #on UCF write (assumed if you have a pin named out1) NET "out1" LOC = "L13" | IOSTANDARD = LVTTL | PULLDOWN #LOC = pin location #IOSTANDARD = standard operation #LVTTL = for 3.3v operation #PULLDOWN = for connecting a pull down resistor
#on UCF write (assumed if you have a pin named out1) NET "out1" LOC = "L13" | IOSTANDARD = LVTTL | PULLDOWN #LOC = pin location #IOSTANDARD = standard operation #LVTTL = for 3.3v operation #PULLDOWN = for connecting a pull down resistor