jayTudu
Member level 1
Hi frnds,
If some one have tried using lsi_10k or other lsi libraries in synthesinzing design using synosys DC he might have faced the problem either dring the time of simulation using VCS or may be during the time of test pattern generation using TetraMax.
I am facing the similar kind of problem while generating test unsing TetraMax. And the reason is simple, because the cells those are their in lsi_10k.db file are used during syntheisizing but there is
no source file(.v or .vhdl) file provided by synopsys for lsi libraries.
Does any one of you have any source file of these libraries or any references where can these
are available ?
PreThanks,
Jay ...
If some one have tried using lsi_10k or other lsi libraries in synthesinzing design using synosys DC he might have faced the problem either dring the time of simulation using VCS or may be during the time of test pattern generation using TetraMax.
I am facing the similar kind of problem while generating test unsing TetraMax. And the reason is simple, because the cells those are their in lsi_10k.db file are used during syntheisizing but there is
no source file(.v or .vhdl) file provided by synopsys for lsi libraries.
Does any one of you have any source file of these libraries or any references where can these
are available ?
PreThanks,
Jay ...