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SOT23 Package Thermal Consideration

berger.h

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I want to use NMOSFET transistors in a SOT23 package for switching the load.
In connection with that, I started to solve how far the heat from the SOT23 can be dissipated by the copper on the PCB.
Somehow I can't find relevant information, if I found anything at all it was related to SOT23-6 or 5.
Can you advise?
 
Hi,

usually the datasheet of the MOSFET provides sufficient information, to make at least an adequate estimation. Which MOSFET are you using?

NR
 
Hi,

I agree that the datasheet should be the first place to look for informations.

But regarding spreading of heat .. it more relates on PCB. Layer stackup, copper thickness, thermal vias ...

So you have two "thermal resistances" in series. The higher resistance is the one that needs to be optimized.

Klaus
 
OK let's take a look at the AO3422 datasheet
All I see there is Maximum Junction-to-Ambient Typ 115 max 150 C/W.
and in the notes:
The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The
value in any given application depends on the user's specific board design.
the transistor itself has the most heat on the center pin (here drain), so it can flow through this pin to the copper on the PCB, and then there is a dependence of the copper surface on the thermal resistance of the entire SOT-23 + PCB assembly.
For other types of SMD housings, it is not a problem to find temperature resistances for at least several copper surfaces around the housing.
 
Hi,

such statements are quite common. Usually the thermal resistance is stated for two different kind of boards/footprints & copper thickness.
Here the question is, what's your application? Steady current or switching application? For a switching application figure 10 & 11 would provide more information.

BR
 
Conservatively, you don't want to operate at max temperature and heat up other parts on the board or accumulate internal ambient rise and forget about assumptions like air circulation. Every OEM may have their own set of assumptions for MTBF, 2 oz copper area ( which doubles the cost of high volume PCB) but you find lots of datasheets in DK for SOT23's with specs. Sort by case type then sort by power dissipation. Typically these are rated with 2 oz copper with and without heatsink .

Consider 250 mW max @ 25'C then derate for max ambient for your estimate for all SOT23 then consider 240 'C/W rise using std pads and 180 'C/W with 1 sqin 2x sided 2 oz Cu or 150 'C/W with 1.5x1.5" 2 oz 2s. For 0.25W resistors, derate 50%, you don't want brown stains around the PCB. It's wiser to reduce RdsOn and choose conservative max junction temperatures.

1701553624737.png
 
It's a messy problem and you would probably find your
answer faster by measurement on a representative layout
(or variations). Much of the heat will go out the leads and
board copper (unless you find a heat-slug SOT23, which
is too small for one I think).

You can do this with a stout enough function generator
or other bang-bang driver / lashup.

Turn the FET on with your representative load (you could
vary pulse widths to examine the thermal time constant,
which is important to low duty cycle narrow pulse applications
(close-in features heat up quick, the leads slower, board
slower still - at the board, it probably looks steady state
but at the on-die weakest link, it's temperature-toggling).

At end of stress-pulse, take the drain below body/source by
a fixed current (this can be always-on, trivial). A fixed current
on the body diode can be mapped to temperature by a
brief series of forced-temp measurements. Now you can
get the on-die temperature rise for any condition you like.

This is how we measured package thermal impedance in
new package development. A diode mounted inside, heat,
measure. Badda-bing (if you already had the diode Vf@Iforce
tempco, which we did - our packaging department probably
developed dozens per year, and the diodes are free in the
PCMs on wafer-saw blue film scrap).
 

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