11= WDT enabled in hardware; SWDTEN bit disabled
10= WDT controlled by the SWDTEN bit
hello,
you activated WDT in hardware, and you must handle the watchdog (Clear WDT in your application in a certain time)Code:11= WDT enabled in hardware; SWDTEN bit disabled
else you will go to Reset
In your application , you have the choice to handle or not the watchdogCode:10= WDT controlled by the SWDTEN bit
so, if your choice ...
i don't know this PIC ...
see configuration bits for hardware WDT enable
and datasheet ..
SWDTEN: Software Enable or Disable the Watchdog Timer bit,
1 = WDT is turned on,
0 = WDT is turned off (Reset value),
This bit has no effect unless the Configuration bit, WDTEN<1:0>, is set to 10b (SWDTEN enabled).
You can considere a maximum of silence duration : no exchange of data between the 2 equipements
ito survey your application.. no link with watchdog..
Watchdog is used only to survey the duration of a main looop in your program..
if you don't clear the watchdog in this loop => reset !
With this way, your program can be OK, but not the data exchange..
With dialogque between 2 PLC , we use a "bit de vie" as watchdog
The first PLC set a bit into the second PLC
the second PLC must reset this bit and send back to the first PLC
After a maximum delai , the first PLC test if the bit is cleared or not to declare
link is OK or not.
Are you using an exchange data protocole bewteen PIC and PC ?
so
WDTEN is definied into Confiig2H register
WDT enable=1
set your value of timer watchdog into CONFIG2H
watchdog postcaler select bits
see previous diagram !
and use clrwdt in your main loop...
if your PIC application is blocked into a loop
you will have a reset after WDT timer elapsed..
see post #14Is this time configurable?
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