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some questions about post-simulation

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lhlbluesky

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about post-simulation

i have some questions about layout post-simulation:
1, in options, if i choose R+C+CC, and no inductance, the simulation results will be ok?
2, including or no including inductance(not in high frequency) when post-simulation, what's the difference between them? and which one (including or no including ) will be more realisitic? which one should be used normally for general circuit and layout?
3, there is another option: parasitic reduction. generally, i don't choose this option.and will the simulation results differ much for choosing or no choosing this option? if i choose this option, then parasitic caps and res will be less than actual layout, then are the post-simulation results reliable?
4, if i get 12 bit resolution for layout simulation, then, after fabricated, usually, the measured results will be worse than the post-simulation. but, what extent will it be? and mostly, what is the performance difference or degradation between post-simulation and actual measurement?

pls give me some reference or advice, thanks all.
 

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