some problems about pipeline ADC

[winsonpku]

i am confused by some problems
i want to know the difference between the S/H(sample and hold circuit)'s load and the the SHA(sample and hold amplfier,the amplifier used in the S/H)'s.
they are the same thing in my opinion.but we konw that the sampling capacitor maybe part of the S/H's load.if we do the S/H's simulation and the SHA's simualtion,we give the output load different parameters?!
how to use the capacitor to set the VTH of the comparator?
who can give me some papers or books that will give me answer.
thanks first!

 

[ezt]

Hi.
Assume we have a Cs (sampling cap.) and a Cf (feedback cap.) in our S/H circuit. Ciop is the input cap. of our Opamp and Co is the sum of Opamp output cap. and the input cap. of the next stage. Then we have

Cload = Co + (Cf *(Cs+Ciop)) / (Cf+Cs+Ciop)

So when you are simulating just the Amplifier in S/H, you should use the whole Cload as the load cap. of your circuit. But when you are simulating the S/H circuit, i.e. Cs and Cf exist in your circuit, you should use just Co as the load cap. of your circuit.

Regards,
EZT

 

[simon110]

if you simulate the S/H in pipeline adc, I think you should include the capacitance of SC-CMFB and the input capacitance of comparator,so

CL=Cnext+Ccom+Cout+Ccmfb+Ceff

Cnext:the sample capacitor of next stage
Ccom:the capacitance of comparator
Ccmfb: the capacitance of SC-CMFB
Ceff: Cs*Ci/(Cs+Ci)--flip around S/H
(Cf *(Cs+Ci)) / (Cf+Cs+Ci)--Charge transfer s/h

as for the threshold voltage of comparator you can read the paper:
"A 1.5-V 10-bit 14.3-M CMOS pipeline analog-to-digital converter"