some new trend topic in low power vlsi

[renoz]

hi



please give me some new trend topic in low power vlsi

thankz advance

 

[mirrobbs]

Algorithm optimization, Low voltage, Multi-voltage, Pipelined/ Parallel Architecture, Low power logic cells, New devices(3D transistor)...

 

[yadavvlsi]

There are various techniques for low power VLSI design.
1. Reducing chip and package capacitance: This can be achieved through process development such as SOI with partially or fully depleted wells, CMOS scaling to submicron device sizes, and advanced interconnect substrates such as Multi-Chip Modules (MCM).This approach can be very effective but is also very expensive and has its own pace of development and introduction to the market.
2. Scaling the supply voltage: This approach can be very effective in reducing the power dissipation, but often requires new IC fabrication processing. Supply voltage scaling also requires support circuitry for low-voltage operation including level-converters and DC/DC converters as well as detailed consideration of issues such as signal-to-noise.
3. Employing better design techniques: This approach promises to be very successful because the investment to reduce power by design is relatively small in comparison to the other three approaches and because it is relatively untapped in potential. This includes clock gating, power gating, using multi-Vt cells in design and back-biasing to reduce leckage.
4. Using power management strategies: The power savings that can be achieved by various static and dynamic power management techniques are very application dependent, but can be significant. It includes adding sleep mode and power down modes in the design.

Trends in Low-Power VLSI Design
**broken link removed**
ASIC-SoC-VLSI Design: Clock Gating
ASIC-SoC-VLSI Design: Power Gating

 

[mirrobbs]

You can also refer to book of Jan Rabaey: “Low Power Design Essentials”.