some interview questions--answer needed

[sp3]

siso interview questions

Hi all,

Below are some Interview questions. I need your answers/thoughts for those. Plz reply for these:

1.What happens to the VTC of a CMOS inverter if Vdd is reduced ?

2. What is the optimum value of Vdd for a CMOS inverter ?

3. A CMOS inverter has it 's o/p fed back to it 's input. What will be the function of the ckt?

4. How to Swap two 8-bit registers without using another register ?


Thanks,
sp3

 

[laseetha]

xchg in verilog

i think ur fourth question is from microprocessors . for 8085 microprocessor there is an instruction called XCHG - which swaps the contents of HL register pair with DE register pair without using any intermediate registers

 

[hock]

ANS3 circuit will oscillate with a time period controlled by the prorogation delay.

 

[pandit_vlsi]

Answer for the 4th Question:

Assume that two register are 8 bit long. Connect the output of first register to the input of the second and connect the output of second register to the input of the first.
Now do the left shift or right shift 8 times.


Regards,

Pandit.M

 

[gliss]

For the Forth question you can use a memory location

 

[kulkarni_saurabh]

Answer to the 4th Question:

In Verilog this can be done by using non-blocking assignments.

always @ (posedge clk or posedge rst)
begin

  if (rst == 1'b1)
  begin
    q0 <= <q0 rst. value>;
    q1 <= <q1 rst. value>;
  end

  else
  begin
    q0 <= q1;
    q1 <= q0;
  end

end

Hope this helps.

 

[sachin_kirdat]

ANS3 circuit will oscillate with a time period controlled by the prorogation delay.

--> It will not oscillate for single inverter, if you connect 3,5,7 inverters then only you will see osc. other wise output will be some dc voltage. If ur inverter is designed to have Trise=Tfall then you will get vdd/2 at input as well as outputs.

 

[vikram789]

As far as optimum value of Vdd is concerned i have read ( in sedra & smith) that new technolgies are being implemented with Vdd as low as 1V coz it will decrease the figure of merit(speed power product) but keeping in mind that tp is not increased as tp is inversely proportional to Vdd.

sachin please explain ur answere as even i think it should oscillate with period = tp

 

[venkat_kode]

Ans3

it acts as oscillator with period:T = 2 * tp if 2tp >> tf + tr.

"If this condition is not met, the circuit might not oscillate—one “wave” of signals propagating through the inveter will overlap with a successor and eventually dampen the oscillation"

 

[sachin_kirdat]

Vikram,
ideally ur correct by this should oscillate at 2*tp period, but in actual it does not happen you can check it out with HSPICE. I do not know why it does not osc.

 

[ytliang]

Ans3
It does not oscillate.
The open-loop circuit contains only 1 pole (provides a max frequency-dependent phase shift of 90 degree). Since the inverter exhibits a dc phase shift of 180 degree due to signal inversion, the max total phase shift is 270 degree. The loop therefore fails to sustain oscillation growth (need 360 degree).
(Razavi p.484)

To build an oscillator with inverters, u would need at least 3 inverters.

 

[speedforu]

ans 4 :
r1 = r1 xor r2;
r2 = r1 xor r2;
r1 = r1 xor r2;

 

[saro_k_82]

1. What is VTC?

2. Optimum in what sense? For optimal power dissipation, it should be VTN+VTP but gives poor speed.

3. The inverter will be biased at it's trip point. It is just like connecting a diode connected NMOS to a diode connected PMOS. How can it oscillate?

 

[dexter_ex_2ks]

1) VTC I believe is for Voltage Transfer Characteristic, u know it (if not search the net). I believe it will not be so sharp.....
2) As for the optimum voltage , hmmm,I think it should be higher than Vthn+Vthp(so in high-out -> PMOS will be in strong-inversion, and low-out -> NMOS PMOS will be in strong-inversion), and as for upper limit, I think as much as the technology can support (possible that the leakage current will increase ).
3) No way it will oscillate because if we short in-out, we'll get 2 saturated transistors connected together from VDD to GND (or VSS), driving a lod of current from Vdd to Gnd, no oscillation cause of Cgs of the transistors.
4) As for registers -> very good replies so far.

 

[teteamigo]

Hi all,

Below are some Interview questions. I need your answers/thoughts for those. Plz reply for these:

1.What happens to the VTC of a CMOS inverter if Vdd is reduced ?

2. What is the optimum value of Vdd for a CMOS inverter ?

3. A CMOS inverter has it 's o/p fed back to it 's input. What will be the function of the ckt?

4. How to Swap two 8-bit registers without using another register ?


Thanks,
sp3

1-IF sizes (W/L) of FETS remain constant, and input swing reduces too with VDD, then the main problem is reducing the slope of linear region and the inflection point=VDD/2 of VTC, because ID saturation of NMOS&PMOS (short-circuit VDD to GND) diminuishes.

2-VDD is related with voltage thresholds of FETS (VTH<<VDD). Scaling one need to changing the other. VDD influence the propagation delays.

3-If the output is shunted with input, the function of circuit is a BIAS source with VDD/2

4-"An exchange of one thing for another"

If the registers are like SISO just link it together , and transfer the bits with clock.