1. Verilog HDL is a native parallel programming language.
2. Therefore it is possible to model/run and simulate any parallel programming concepts (no matter of Digital or analog) with Verilog HDL.
I want to talk with anybody interested in this area.
I think it is more important that it seems.
It may be obvious just like many other things, but
What did you think about a class project that in you are requested to model a parallel system (like a queue-based situations in banks, bus-stops, etc.)
I think the parallel programming native of verilog may be used to model
and simulate such situations in a very fine fashion by you as a HDL talent engineer.