fan1200
Newbie level 6
I am new in DC and have some questions.Plz help me.
I want to change verilog HDL to the netlist,then change the netlist to layout.
Now I use design vision to change verilog HDL to the netlist.
Here is the first question.When I DC the circuit ,there is an Error:Could not read the following target libraries:your library.db
Can I get the library from the foundry or synopsys?
The second question:
I design a counter which has 2 clocks of the same frequency but with a phase difference.When I DC it ,the clock_ and reset_ are floating(They don’t connect to any other net ).Is there something wrong with the verilog HDL which I wrote?
Thank YOU so much.
I want to change verilog HDL to the netlist,then change the netlist to layout.
Now I use design vision to change verilog HDL to the netlist.
Here is the first question.When I DC the circuit ,there is an Error:Could not read the following target libraries:your library.db
Can I get the library from the foundry or synopsys?
The second question:
I design a counter which has 2 clocks of the same frequency but with a phase difference.When I DC it ,the clock_ and reset_ are floating(They don’t connect to any other net ).Is there something wrong with the verilog HDL which I wrote?
Thank YOU so much.