I am new in DC and have some questions.Plz help me.
I want to change verilog HDL to the netlist,then change the netlist to layout.
Now I use design vision to change verilog HDL to the netlist.
Here is the first question.When I DC the circuit ,there is an Error:Could not read the following target libraries:your library.db
Can I get the library from the foundry or synopsys?
The second question:
I design a counter which has 2 clocks of the same frequency but with a phase difference.When I DC it ,the clock_ and reset_ are floating(They don’t connect to any other net ).Is there something wrong with the verilog HDL which I wrote?
fan1200 I didn't get you.. I think you got confused.. There is ofcourse standard flow/process to generate netlist..
Generally target_library should point to the library provided by your silicon vendor.. Couple of libraries from LSI, TSMC come embedded with DC which can be found in the path.. During mapping DC will Choose functionally-correct gates from this library and Calculate the timing of the circuit using vendor-supplied timing data for these gates
On the other hand link library is used to resolve sub-design references.. hope now it clears your doubt.
So if you have a vendor specific library.. you should set these env variables to point them
I design a system which has to use differential signal .So before the counter there is something whose output signals are differential signals as input signal in the counter.