some basic questions - additions , relational condition

[madmaiden]

some basic questions

hello,

I have some basic question and reading different tutorials didn't help. I want to make a state machine that goes though all states a fixed numer of (let's say five) times then stops and waits until a button is pressed. I tried coding this in verilog and also in vhdl. no results. In order to test if the state machine was working i connected it to the tx pin, and every time it reached the first state a number was transmitted. It workes fine, but I want to make it transmit five values every time a button is pressed, no more no less. I have also a debounce block, that works fine.
I will post the code written in vhdl:

fsm1: PROCESS (pb1,currentstate,tx_rdy,nr)
begin
     case currentstate is
         when idle =>
               tx_write<='1';
               if (tx_rdy='1') AND (nr<5) then
                    nextstate<=st1;
               elsif  (pb1='1')
                    nr="000";
              else
                   nextstate<=idle;
              end if;
       when st1 =>
             dat<="01010001"; --doens't really matter what it is transmiited for now
             nr<=nr+'1';
             nextstate<=st2;
       when st2 =>
             tx_write<='0';
             nextstate<=st3;
       when st3 =>
             nextstate<=idle
   end case;
end process;

I tried different methods of checking the relation. None works, either it cycles though an infinite number of times, or none. I tried also sending nr to the PC, and the number I recieve are not consecutive.
How are additions performed?
How is a relational condition evaluated?

thank you,
Dinu.

 

[radix]

Re: some basic questions

madmaiden,

A couple of things:

1) Your process is a combinatorial block. Any signals that you specify in any of your branches must be fully specified or else you're implying latches, which is probably not what you want. You can specify a default value for these signals between the begin and case statements.

2) I assume you have a sequential process somewhere that is registering the value of nextstate into currentstate?

3) It might be useful if you include some of your signal declarations.

Radix

 

[nickagian]

Re: some basic questions

madmaiden,

I don`t get much from your code, since you haven`t included any signal declarations. However, I guess that the 'nr' signal is of type integer. Assuming this, at state 'st1' you should not do

nr <= nr + '1'

but

nr <= nr + 1

Above that, be very careful with what radix said under point (1). For example, at 'idle' state, under the elsif branch, you don`t declare at which state the FSM goes. Moreover the 'tx_write' and 'dat' signals should take a value at each state. You can either do what radix proposed or assign at the beginning of each state a value for both signals.