Some basic questions about Quartus

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Slava_

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Hello everyone,
I have some questions about Quartus II(v. 9.1):

1. May I determine in any place in program to run a "simulation without pin assignments", in order to prevent warnings?

2. I run a compilation and now I have to "analyze a critical path". How to do it? And what is it?

3. Where I can find a "logic usage (Combinational and Flip-Flops)"? Is it in "Flow Summary"?

Thanks in advance,
Slava.
 

Q1 and Q3 can be answered best by playing around a few minutes with Quartus...
For Q2, you have to understand the concept of FPGA timing analysis and operation of the respective tools. You can however start with "location of critical pathes" in the Quartus online help to get an idea.
 
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