SoC Encounter and issues regarding the RTL Synthesis step

[Kulprashant]

SoC Encounter

Hi Friends,
i am working on SoC Encounter which is Place & Route tool in which u can do RTL Synthesis also. so i would like to know some issues regarding the RTL Synthesis step,
Basically i will get Gate level Netlist from the PKS tool & same netlist i wiil use input to the SoC Encounter.
So i want to know what r effects of
1) design for test configuration step
2) Scan Insertion step
3) JTAG/BIST Generation step

Note : from PKS, i want only Gate level Netlist , so is it necessery above 3 steps.

Regards,

Prashant