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SOA of FET?

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cupoftea

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Not surprising, most FETs optimized for switching performance don't fare well when operated in saturation for any significant amount of time. Often they won't even show a curve for 100ms because it's basically identical to the DC curve.

But other families of FETs are still optimized for SOA in saturation, and you will see more difference between 100ms and DC. For example here's a device I used in an inrush limiter/load switch circuit. Current handling is ~3x higher at 100ms than at DC.

The catch is that those curves assume the case temperature is held perfectly at 25C. With a real heatsink, those curves will get closer together.
 
Even the DC line given above is a thing to be taken carefully, as from the graph the limit is 2v5 @ 100+A = 250+ watts,

this is only possible by keeping the junc to 25 deg C, i.e. the heat flow thru the die is enormous and these tests are rarely performed in the real world as the cooling mechanisms required are quite involved - instead they are calculated from die size and method of soldering the chip down.

In the real world any sort of cyclic operation to the 250W point and back to lower powers would cause die failure due to mismatch of TCE in the layering of components ... - unless the junc could be firmly held to 25deg C under all conditions ( unlikely ).
 
SOA chart artifacts sometimes come from letting people
who didn't do the experiment, make the pretty chart. If
there is no intervening data point, sometimes a line gets
drawn solid anyway.

Getting "1 second", "10 second", "100 second" data
takes extra time and yet yields not much value except
for a few kooks looking for abnormally high short circuit
event durations. 100ms will get you past the "screwdriver
short" scenario. The device maker doesn't probably care,
or want to do anything special to support, worse abuse
cases that nobody else has asked for.

If your chop rate is more than (say) 10/thermal_time_constant
and your pulsed power dissipated in the part less than (say)
10X steady state rating, then time averaged can be treated
the same as steady state. If you have a further-out scenario
then the experiment probably falls to you.
 
Even the DC line given above is a thing to be taken carefully, as from the graph the limit is 2v5 @ 100+A = 250+ watts,

this is only possible by keeping the junc to 25 deg C, i.e. the heat flow thru the die is enormous and these tests are rarely performed in the real world as the cooling mechanisms required are quite involved - instead they are calculated from die size and method of soldering the chip down.

In the real world any sort of cyclic operation to the 250W point and back to lower powers would cause die failure due to mismatch of TCE in the layering of components ... - unless the junc could be firmly held to 25deg C under all conditions ( unlikely ).
SOA curves are specified with the case temperature Tc fixed, not the junction temperature Tj. At least I've never seen it with a fixed Tj. Generally I expect that the curves are based on empirical data where devices are tested to failure, with some derating factor applied.

But now that I think about it, I'm not aware of any actual standard on SOA ratings, which is odd.
--- Updated ---

Also just realized in my original post the datasheet actually doesn't have a 100ms curve, the labels are just placed in a very confusing way. Here's an example of another device which actually does have a 100ms curve. Again, this is a device which has been optimized for operation in saturation.
 
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It can be difficult to determine after the fact, how the reliability
experiments were conducted and what the limit-criteria were.

You might decide that Tj=175 is one "wall" and measure Tj
through one of the exposed diodes, and this might be what
clips off the upper right SOA corner despite no actual failure at
test - simply violating abs max die temp by electrical power in,
thermal power out.
 
It can be difficult to determine after the fact, how the reliability
experiments were conducted and what the limit-criteria were.

You might decide that Tj=175 is one "wall" and measure Tj
through one of the exposed diodes, and this might be what
clips off the upper right SOA corner despite no actual failure at
test - simply violating abs max die temp by electrical power in,
thermal power out.
IMO this is also a valid way to determine SOA specifications, though in practice measuring or simulating hot spots on the die is not easy at all. I would hope that actual testing is done to verify that no actual failures occur within the SOA. But again, I'm not aware of any standards regarding this. Maybe I'll ask some FAEs about this.
 

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