Hi,
In the 1st ckt, the diode connected is on nmos+res side, which will lesser vgs, when compared to vgs of the other nmos device. This means higher current in the nmos on the left arm wrt to nmos+res branch. This increase in current in the loop makes the nmos node go close to vdd & the pmos gate goes very close to gnd. This is the reason for large current through p1,n1 as the start up branch is kind of resistive divider.
---------- Post added at 09:33 ---------- Previous post was at 09:06 ----------
by feedback analysis, initial positive fb(with 0 current) is same order for both the loop, but with some current the 1st ckt settles with +ve gain of ~gm*rds, which is high enough for the negative loop (by the resistor) to compensate. In the second ckt the loop gain with some current is around 1/(R*gm), which is easy for the R to compensate, thus the current stabilizes.