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So similar circuits, why one start-up module cannot work as I expect ?

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whitemoustache

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Hello everyone, the circuits above puzzles me a lot...
The only difference between the 2 circuits are the mirror directions, except the resisters and NMOS in black circles are set in order that that the loop of the current reference is OK.

However, the second circuit works good, while the first one has trouble with start-up. Particularly, most current in P1 flows into N1, and the whole circuit stablizes in a wrong state.

What courses this? And i wonder what can confirm a circuit not being like this ?8-O
 
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whitemoustache

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I'm so sorry that I don't know how to show that illustration big and clear in the thread, plz click it and watch....
 

sushanth

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Hi,

In the 1st ckt, the diode connected is on nmos+res side, which will lesser vgs, when compared to vgs of the other nmos device. This means higher current in the nmos on the left arm wrt to nmos+res branch. This increase in current in the loop makes the nmos node go close to vdd & the pmos gate goes very close to gnd. This is the reason for large current through p1,n1 as the start up branch is kind of resistive divider.

---------- Post added at 09:33 ---------- Previous post was at 09:06 ----------

by feedback analysis, initial positive fb(with 0 current) is same order for both the loop, but with some current the 1st ckt settles with +ve gain of ~gm*rds, which is high enough for the negative loop (by the resistor) to compensate. In the second ckt the loop gain with some current is around 1/(R*gm), which is easy for the R to compensate, thus the current stabilizes.
 

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This means higher current in the nmos on the left arm wrt to nmos+res branch.
---- Not really. As a matter of fact, W/L of the NOMS in the right side is larger than the left one, and accordingly there is a balance point if the reference works normally.

This is the reason for large current through p1,n1 as the start up branch is kind of resistive divider.
---- If Gm of NMOS+RES is larger than the left NMOS, then what you describe would happen. But in fact Gm of NMOS+RES is set to be less than the left NMOS, so this did not happen in the simulation.
In fact, if NMOS node goes close to VDD, then N1 would be surely shut down.
The problem is the NMOS node is not in a so high potential, and accordingly N1 is not shut, and too large current flows from P1 to N1.

Thank you very much for replying ! :-D
 

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