N
nks7 said:is there any formula for designing a cmos logic gate for any given function with smallest no of transistors
golfbumb said:Yes, there is a rule of thumb for minimizing the number of CMOS transistors in a design.
For every inverter required in your design it takes two transistors. A non-inverting buffer capable of full Vdd to Vss swing takes four. For each nand or nor gate it takes 2*n transistors for every inputto the gate you are designing. For example, a two input NAND takes 4 transistors, a three input NOR takes six, and eight input NAND takes 16 and so on.
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