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Small UHF PLL, "ringing" when I touch VCO box

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Nov 27, 2001
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Hello !

I built small UHF PLL and some how it works, but, its "ringing" when
I touch VCO box, or ground arround VCO .

VCO is divided by 64 and by 420-440 , step 1Mhz.
Ref. freq is 15.625Khz (16Mhz/1024)

Any idea what Im doing wrong ?
PLL filtering ?



loop bamdwidth

Your reference frequency is so low that the loop bandwidth must be small. It will not correct frequency variations that are more rapid than the loop bandwidth.

Try raising your reference frequency so that you use a smaller divide ratio and also a wider loop bandwidth.

How have you designed/analyzed your PLL/loop filter? You may have a system that is very unstable and close to oscillation. Did you use some software to do the analysis? Let us know what you have done so far and we will see if we can help. I usually use the PLL program in E/A/G/L/E/W/A/R/E to accomplish the design and analysis.

Go to national site **broken link removed** and you'll find a PLL filter design program on this site. Use it and find correct filter component value for your PLL.

Be sure about VCO gain , because it is very important.
Ringing may occur due to too wideband PLL filter or synthesized frequency may outside of the VCO range. It tries to lock but VCO doesn't want :lol:

Regards ,

Thanks all for interesting answers !

For design I used piece of paper and pencil.
Havent any simple (!) and good software for that.
PLL can lock, not too fast but that is not problem.
When I listen signal on control receiver, in FM mode its noisy,
in ssb mode its totaly unusable, sounds like bird.
Ill try to calculate filter with some tools, maybe Ill get better results.

Maybe I have to use some finished project but hard to find what I need.

uhf pll

Looks like you reduced the loop bandwidth to make it work and in this way it does not correct the noise due to the power supply and the noise picked up by the varicap control voltage.
Looks like the VCO gain is very high and so any microvolt in the varicap voltage is translated into noise.
As the other people i suggest to reduce the division ratio and to increase the loop bandwidth.
Take care that the modulating signal must have the lower frequency at least 10 times the loop bandwidth to avoid corrections from the pll loop.
Take also a lot of care filtering the power supply and the grounding.
A very good program for PLL calculation is from NATIONAL, at the address specified above.
Hope to be helpful.


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