Slice usage in XC2V1000-4FG456 FPGA

Hi all,
I have a small querry, it might be related to FPGA basics but i am unable to resolve it even after going thru a lot of docs. In a small module in VHDL, i am using shift -shl & shr as-
entity res is
port( x0 : IN integer;
x1 : IN integer range 0 to 31;
----
-----
end;

ARCHITECTURE shft of res IS
BEGIN
res_out <= conv_integer(
shl(conv_std_logic_vector(x0, 32),
conv_std_logic_vector(x1, 32) ))
when (Op = 0)
else conv_integer(
shr(conv_std_logic_vector(x0, 32),
conv_std_logic_vector(x1, 32) ))
;
END shft;

Now, my range of count i.e. is constrained from 0 to 31, but when i change
conv_std_logic_vector(x1, 32) to conv_std_logic_vector(x1, 5), the slice count increases from 165 to 178. Though the difference is slight but accordingly Slice usage should decrease. Plz correct me if i m wrong. I might be missing something.
My question is "Why is Slice count increased, coz on count=32 my range for x1 is still 0 to 31, and constaining count=5 range x1 0 to 31 is more defined?"
Thanks in advance.