Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

skew and slew limits of design

Status
Not open for further replies.

vikramc98406

Full Member level 1
Joined
Nov 30, 2007
Messages
97
Helped
8
Reputation
16
Reaction score
6
Trophy points
1,288
Activity points
1,939
Can anyone give me details of factors deciding for SKEW and SLEW and INSERTION delay for a design?
 

Hi,

Well Insertion delay is mainly done to achieve tolerable skew. and the tolerable skew will tell u abt the driving schemes. Driving schemes will define how ur buffers are inserted in interconnects. For this pls refer Low power Design by Yeap.

Slew: The rate of change of voltage. this in turn is dependant on the circuit RC component.

regds,
anup
 

u need to balance the insertion delay for different clocks to min. skew
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top