SISO design using behaviourial modeling in verilog

I have written verilog code for 4 bit Serial in serial out.

module siso(
input clk,reset,in,
output reg [3:0] out);
reg [3:0]temp;
always @ (posedge clk)
begin
if (reset)
begin
out <= 0;
temp <= 0;
end
else
begin
temp[0] <= in;
temp <= temp << 1;
out <= temp[3];
end
end
endmodule

output is coming 0000 and even in temp input is not loading. I am not understanding why its happening like this.

if i swap the statements
temp[0] <= in;
temp <= temp << 1;
as
temp <= temp << 1;
temp[0] <= in;
output is coming.
PLZ tell me why its not working with the previous structure. :idea:

Thanks in advance

Shifts a 0 into the LSB.
You should code a shift register like this...
Which does the exact same thing as this...
Which will work regardless of the ordering of the assignments.

Regards

ads-ee said:

Code:

temp <= temp << 1;

Shifts a 0 into the LSB.
You should code a shift register like this...

Code:

temp <= {temp[2:0], in};

Which does the exact same thing as this...

Code:

temp[0] <= in;
temp[1] <= temp[0];
temp[2] <= temp[1];
temp[3] <= temp[2];

Which will work regardless of the ordering of the assignments.

Regards

Click to expand...

thanks for the reply but i have checked with the same after swapping both the statement it is not giving the output.

dkvlsi said:

thanks for the reply but i have checked with the same after swapping both the statement it is not giving the output.

Click to expand...

What statements are referring to? Post the code.

ads-ee is correct....
just check this code.....

always @ (posedge clk)
begin
if (reset)
begin
out <= 0;
temp <= 0;
in <= 1'b1; //just for testing make it "1"...
end
else
begin
//$display(" value of in %d",in);
//temp[0] <= in;
//$display(" value of temp[0] %d",temp[0]);
//temp <= (temp << 1);
temp <= {temp[2:0], in};
$display("value of temp %b",temp);
out <= temp[0];
end
end

it's working very fine.....

I think to reflect SISO operation...

module siso(
input clk,reset,in,
output reg out );
reg [3:0]temp;


always @ (posedge clk)
begin
if (reset)
begin
out <= 0;
temp <= 0;
//in <= 1'b1; //just for testing make it "1"...
end
else
begin
temp <= {temp[2:0], in};
//$display("value of temp %b",temp);
out <= temp[3];
end
end
endmodule