single ended clock termination topology - need help

[Anuradha Bahl]

Hi,
I have a single ended LVCMOS clock signal (source termination 50 ohms) splitting into 4 single ended LVCMOS clk signals for 4 SDRAM chips. How do I terminate each of the 4 clks so that they are clean? Please point me to the correct formulas to calculate the termination.
I am thinking of a thevenin termination about 110ohms resistor to VCC and gnd.

Please help.

 

[otherguy]

Hi,
I have a single ended clock signal (source termination 50 ohms) slitting into as 4 single ended clk signals for 4 SDRAM chips. How do I terminate each of the 4 clks so that the Zo is ~ 50 ohms looking from both sides of the network? Please point me to the correct formulas to calculate the termination.
I am thinking of a parallel termination about 80-100ohms resistor to gnd.

Please help

Don't you need 4x200 Ohms in parallel to make 50 Ohms?

 

[karesz]

Hi,
If you has a source with 50 Ohm & 4x load on that=your clk lines have to be 200 Ohms, other question is if you load it per thevevin or simple II resistors...
K.