Strictly spoken, tpd hasn't to do with waveforms, only rise- and fall-time matters. But of course, they are partly related, when comparing logic families.
I still think, that the said sine waveforms are a case of unsuitable probing. As already said, you need very short ground connection (directly to the "coaxial" tip connector) with standard passive probes. If you are frequently facing similar measurement problems, you should think about a low capacitance active or passive resistive probe. Even a 10:1 or 20:1 divider formed by a chip resistor and a 50 ohm coax cable connected to the 50 ohm oscilloscope input can be a reasonable alternative.
Also insufficient supply bypassing of the logic gate can be a reason to get bad waveform.
Regarding FPGA interface, I would prefer a differential I/O standard if you can't assure sufficient voltage swing. I have also used external LVDS receivers as level converter. As they are not generally specified for this mode of operation, you have to check the empirical behaviour. Logic thresholds of single ended FPGA standards aren't tightly specified, so you have to provide sufficient input level, on the other hand, the maximum voltage range should be kept safely. Just as an idea, how about a self biased FPGA input circuit using an inverted output and a high ohmic resistor?