sin wave multiplication using IP Cores -

Status
Not open for further replies.
C

Christian Chetcuti

Junior Member level 3
Joined
Mar 12, 2014
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
213
I am trying to multiply 2 sine waves and then transfer the result to a DAC converter. The screenshot below shows the schematic.

The divider is built using the clocking wizard core to get the 100Mhz system clock down to 50Mhz. Next comes the sine wave generators which were built usind the DDS Compiler 4.0. The multiplier was built using the multiplication block (Math function core) and next comes the PMOD DA2 reference component.

After setting up the ports, and clicked on generating programming files this warning comes up:


Do you have any idea how to fix this ?


 

It looks like a harmless warning that you get due to how the BRAMs are used in those DDS cores you use for your sine waves.

First step is to read that Xilinx Answer Record 39999 to be sure what that is about. Second step is to make a small testbench for your design to see if you get the expected sine waves and multiplied results.

So again, I think this is just a harmless warning. But best verify as suggested above.
 
How would I test this schematic? I would only need to declare the system clock value right ? as the other modules are built in cores whose function is that of returning the respective sine wave..
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…