sin wave multiplication using IP Cores -

[Christian Chetcuti]

I am trying to multiply 2 sine waves and then transfer the result to a DAC converter. The screenshot below shows the schematic.

The divider is built using the clocking wizard core to get the 100Mhz system clock down to 50Mhz. Next comes the sine wave generators which were built usind the DDS Compiler 4.0. The multiplier was built using the multiplication block (Math function core) and next comes the PMOD DA2 reference component.

After setting up the ports, and clicked on generating programming files this warning comes up:

WARNINGhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.

Do you have any idea how to fix this ?

 

[mrflibble]

It looks like a harmless warning that you get due to how the BRAMs are used in those DDS cores you use for your sine waves.

First step is to read that Xilinx Answer Record 39999 to be sure what that is about. Second step is to make a small testbench for your design to see if you get the expected sine waves and multiplied results.

So again, I think this is just a harmless warning. But best verify as suggested above.

 

[Christian Chetcuti]

How would I test this schematic? I would only need to declare the system clock value right ? as the other modules are built in cores whose function is that of returning the respective sine wave..