Simulation with HCPL-316j

[dominguesg]

Hello Folks!

I'm trying to simulate a Full Bridge Inverter in PSpice using the HCPL-316j as the driver. I'm using bipolar SPWM, and a simple PWM circuit using AmpOp. The driver is switching the SIHG47N60E MOSFET from Vishay. I'm using the real models from MOSFET and Driver. The problem is: when I try to raise the Vsin (PWM Ref) peak value, 2 drivers start to switch with the two others, and consequently, shorting the MOSFET's. I really need the help of the community because this is my final project to graduate. I don't know what I'm doing wrong. The curves showing the problem folows below:

The circuit is structured on this way: PWM -> Dead Time ->Drivers(1,2,3,4) -> MOSFET's (1,2,3,4) -> LC Filter -> Rload

PWM Circuit:



Dead Time Circuit



Driver:



Full Bridge:



Filter:



This is the curves of input:



Here is the normal operation:



Here is one short in detail:




Every help is wanted! :razz:

Thanks!! :thumbsup:

 

[FvM]

2 drivers start to switch with the two others

Means what, exactly? Where do you see it in the waveforms?

Some important waveforms are missing in your simulation results, e.g. Vds or Vbus. I expect that you primarily see oscillations of MOSFET output capacitance with your artificial 15 nH Vbus ESL.

Possible countermeasures:
- low inductance Vbus bypassing
- asymmetrical gate drive with slower (higher series resistance) turn on

 

[dominguesg]

Hi! Thank you for Replying!

Means what, exactly? Where do you see it in the waveforms?

When I said "2 drivers start to switch with the two others", I meant that in the last waveform I see the red curve (Driver 2) is trying to switch with the green one (Driver 1). But this only happens when the Vsin is close (half or greater) to VTri, e. g. when Vsin = 1.5V and VTrig = 4, this doesn't happen. And there are no short at all.

Some important waveforms are missing in your simulation results, e.g. Vds or Vbus. I expect that you primarily see oscillations of MOSFET output capacitance with your artificial 15 nH Vbus ESL.

Possible countermeasures:
- low inductance Vbus bypassing
- asymmetrical gate drive with slower (higher series resistance) turn on

I'm going to try this countermeasures and post the Vds waveform.

Thanks again!

 

[FvM]

I meant that in the last waveform I see the red curve (Driver 2) is trying to switch with the green one (Driver 1).

Seeing a certain Vgs reaction during rising Vds is normal operation, caused by Cdg. Please notice that Vgs2 (at least the voltage shown in your waveform) is still negative and far from reaching the threshold voltage. But it might be that Vds2 is increasing considerably or even reaches the breakdown voltage by the working of circuit inductances. It would be also interesting to know if your MOSFET model includes package inductances.

The advantage of a simulation is that you can monitor internal transistor model nodes and "see" why things happen. Under circumstances (e.g. with a nonlinear Cds and Cdg capacitance model) the simulation waveforms might be worse than that of a real circuit if the real circuit has more dissipative elements. But the opposite case is probably more likely, the real circuit shows parasitic effects that aren't modeled. Simulation can't be more than an estimation of real effects in both cases.

 

[dominguesg]

But I don't see how is this connected to the Vsin value...