ok they r within an asynchronous process..
the code is here:
architecture Behav of RS232_RX is
type state is (Idle,StartBit,RcvData,StopBit);
signal next_state,current_state : state;
signal Fifo_write :std_logic;--store out
--signal RD: std_logic;--LineRD_in --active high
signal HalfBitCounter : std_logic_vector(7 downto 0);--sample the start bit at the centre
signal BitCounter : std_logic_vector(7 downto 0);--sampling in centre of the rx data
signal DataCount : std_logic_vector(3 downto 0);---track of the bits rcvd
constant PulseEndOfCount : std_logic_vector(7 downto 0) := "10101101"; -- 173
constant HalfPulseEndOfCount : std_logic_vector(7 downto 0) := "01010111"; -- 88
begin
rst
rocess(Reset,current_state,LineRD_in,BitCounter,HalfBitCounter,DataCount)
begin
Code_out <= '0';
Valid_out <= '0';---indicates to store the valid incoming data in the shift register --Enable
Fifo_write <= '0';--write the data from the shift register to fifo if all the bits are rx
next_state <= current_state;
if (Reset = '0') Then
next_state<= Idle;
else
case current_state is
when Idle =>
if (LineRD_in='0')then
next_state <= StartBit;
else
next_state<=Idle;
end if;
when StartBit=>
if (HalfBitCounter = HalfPulseEndOfCount) then
next_state<=RcvData;
else
next_state<=StartBit;
end if;
when RcvData=>
if (BitCounter = PulseEndOfCount) then--173
Valid_out<='1';--indicates valid data
Code_out <=LineRD_in;--rx data is loaded in code_out->D in shift reg
else
next_state<= RcvData;
end if;
if (DataCount ="0111") then
next_state<= RcvData;
else
DataCount <= (OTHERS => '0');
next_state<= StopBit;
end if;
when StopBit=>
if(BitCounter = PulseEndOfCount) then
if( LineRD_in = '1') then--set when all the data rx is valid
Fifo_write<='1';
next_state<= Idle;
else
next_state<= Idle;
end if;
else
next_state<= StopBit;
end if;
end case;
end if;
Store_out<=Fifo_write;
end process rst;
clking: process(Clk)
begin
if (Clk' Event and Clk ='1')then
if (HalfBitCounter < HalfPulseEndOfCount) then
HalfBitCounter <= HalfBitCounter + 1;
else
HalfBitCounter <= (OTHERS => '0');
end if;
if (BitCounter < PulseEndOfCount) then
BitCounter <= BitCounter + 1;
else
BitCounter <= (OTHERS => '0');
end if;
if(DataCount="0111")then
DataCount <= DataCount+1;
else
DataCount <= (OTHERS => '0');
end if;
current_state <= next_state;
end if;
end process clking;
end Behav;