Simulation warning Xlinx: WARNING:Xst:2170

[sns22]

HI,

I am getting this warning though I have not created too many case states .There are only 4 case statements.

WARNING:Xst:2170 - Unit RS232_TX : the following signal(s) form a combinatorial loop: next_state<3>.
WARNING:Xst:2170 - Unit RS232_TX : the following signal(s) form a combinatorial loop: next_state<2>.
WARNING:Xst:2170 - Unit RS232_TX : the following signal(s) form a combinatorial loop: next_state<1>.
WARNING:Xst:2170 - Unit RS232_TX : the following signal(s) form a combinatorial loop: next_state<0>.
next_state is a temporary variable which I have created to access the states

What danger does it pose to the block of the code?
I dont know why i am getting this warning?

 

[permute]

you have a combinatorial loop. expressions like "x <= y + z" are easy to understand in either clocked or combinatorial processes. the value of x is based on two other known values. "x <= x + z" would make sense in a clocked process, but not in a combinatorial process -- the value of x depends on itself. There would also be no well-defined delay between when x changes, and when the fact that x has changed updates x. if at time 0, x = 1, z=1, what would x be in 10 ns? well, x would be 2, which would mean x would be 3, which would mean x would be 4 ... but there's no mention of the time involved, so really, x could be any value in 10ns.

This probably should have been an error instead of a warning.

 

[sns22]

I have not used but any combinational expressions.
I have used
case current_state is
when case 0=>
when case 1=>
when case 2=>
when case 3=>
end case;

 

[Brownout]

Those can be combanatorial statemets. It depends on if they are contained within a clocked process. It's entirely possibe to get a loop. Why not show us the code?

 

[sns22]

ok they r within an asynchronous process..
the code is here:


architecture Behav of RS232_RX is

type state is (Idle,StartBit,RcvData,StopBit);
signal next_state,current_state : state;

signal Fifo_write :std_logic;--store out
--signal RD: std_logic;--LineRD_in --active high
signal HalfBitCounter : std_logic_vector(7 downto 0);--sample the start bit at the centre
signal BitCounter : std_logic_vector(7 downto 0);--sampling in centre of the rx data
signal DataCount : std_logic_vector(3 downto 0);---track of the bits rcvd


constant PulseEndOfCount : std_logic_vector(7 downto 0) := "10101101"; -- 173
constant HalfPulseEndOfCount : std_logic_vector(7 downto 0) := "01010111"; -- 88

begin
rstrocess(Reset,current_state,LineRD_in,BitCounter,HalfBitCounter,DataCount)
begin
Code_out <= '0';
Valid_out <= '0';---indicates to store the valid incoming data in the shift register --Enable
Fifo_write <= '0';--write the data from the shift register to fifo if all the bits are rx

next_state <= current_state;
if (Reset = '0') Then
next_state<= Idle;
else

case current_state is

when Idle =>
if (LineRD_in='0')then
next_state <= StartBit;
else
next_state<=Idle;
end if;

when StartBit=>
if (HalfBitCounter = HalfPulseEndOfCount) then
next_state<=RcvData;
else
next_state<=StartBit;
end if;

when RcvData=>

if (BitCounter = PulseEndOfCount) then--173
Valid_out<='1';--indicates valid data
Code_out <=LineRD_in;--rx data is loaded in code_out->D in shift reg
else
next_state<= RcvData;
end if;

if (DataCount ="0111") then
next_state<= RcvData;
else
DataCount <= (OTHERS => '0');
next_state<= StopBit;
end if;


when StopBit=>
if(BitCounter = PulseEndOfCount) then
if( LineRD_in = '1') then--set when all the data rx is valid
Fifo_write<='1';
next_state<= Idle;
else
next_state<= Idle;
end if;
else
next_state<= StopBit;
end if;
end case;
end if;
Store_out<=Fifo_write;
end process rst;



clking: process(Clk)
begin
if (Clk' Event and Clk ='1')then
if (HalfBitCounter < HalfPulseEndOfCount) then
HalfBitCounter <= HalfBitCounter + 1;
else
HalfBitCounter <= (OTHERS => '0');
end if;

if (BitCounter < PulseEndOfCount) then
BitCounter <= BitCounter + 1;
else
BitCounter <= (OTHERS => '0');
end if;

if(DataCount="0111")then
DataCount <= DataCount+1;
else
DataCount <= (OTHERS => '0');
end if;

current_state <= next_state;
end if;
end process clking;

end Behav;

 

[Brownout]

Well, one thing I see is there is no way to ever get out of the state RcvData. Also, resetting should be done in the clocked process, and not in the combonatorial one. Try those changes, and if you stil get the mesage, I'll try to take a closer look.

 

[sns22]

yeah i got ur point
i corrected it to

when RcvData=>

if (BitCounter = PulseEndOfCount) then--173
Valid_out<='1';--indicates valid data
Code_out <=LineRD_in;--rx data is loaded in code_out->D in shift reg
else
next_state<= RcvData;
end if;

if (DataCount ="0111") then
next_state<= StopBit;
else
--DataCount <= (OTHERS => '0');
next_state<= RCvData;
end if;
as far as resttin is concerned i have run many other codes with the same coding style and they all work fine.
i tried tht earlier but there is no change in the warning.

---------- Post added at 01:15 ---------- Previous post was at 01:13 ----------

as soon as it will get 8 bits it will come out of the loop else wait for the 8 bits to be rcvd..

 

[Brownout]

That's odd code: I'd try this:

when RcvData=>

if (BitCounter = PulseEndOfCount) then--173
Valid_out<='1';--indicates valid data
Code_out <=LineRD_in;--rx data is loaded in code_out->D in shift reg
end if;


if (DataCount ="0111") then
next_state<= StopBit;
else
--DataCount <= (OTHERS => '0');
next_state<= RCvData;
end if;

I eliminated an unnessary "else" clause, simplifying the code. Taking out unnessary code might help with the warnings.

 

[sns22]

yeah thanks for help!!!!!!!really i need it now...see u later but i m definately havin many more doubts on this...