[SOLVED] Simulation post physical synthesis issue

[rviera]

Hi,

When I perform the logic synthesis in rtl compiler it deletes some "unused" bits, thats ok, I perform the post logical synthesis simulation and the results are still ok. I tell the compiler not to perform the optimization and maintain the bits and the simulation is still OK.

My problem is when I perform the simulation after physical synthesis (encounter). I have some signals in red and the result instead of beying 3E722 is 3E7XX because some bits are unavailable in the multiplier1 and 2, so I thought the problem was with the concatenation, but it doesn't make sense, it works that ways, I can't do "00" & (mul1_A * mul1_B) because I have a number before the multiplication, so I'm in a "deadlock" I don't have any other idea of what is the problem. Is there any command to give to rtl compiler to solve this or it is a vhdl issue?



case cycle is
--THIS IS JUST AN EXAMPLE OF A CYCLE AND HOW THE MULTIPLIER, ADDER AND SUBTRACTOR IS CALLED ON EACH CLK CYCLE
when "0011" =>
mul1_A <= r_b;
mul1_B <= pxplus1;
mul2_A <= r_b;
mul2_B <= pxminus1;
sub1_A <= multiplier1_out;
sub1_B <= multiplier2_out;
r_temp1_next <= multiplier2_out;

at each iteration of the clock I have

process(clk,reset)
begin
if reset='1' then
multiplier1_out <= (others => '0');
multiplier2_out <= (others => '0');
subtractor1_out <= (others => '0');
subtractor2_out <= (others => '0');
adder_out <= (others => '0');
elsif (clk'event and clk='1') then
multiplier1_out <= mul1_A * ("00" & mul1_B);
multiplier2_out <= mul2_A * ("00" & mul2_B);
subtractor1_out <= sub1_A - sub1_B;
subtractor2_out <= sub2_A - sub2_B;
adder_out <= add_A + add_B;
end if;
end process;




Here are my post logical and post physical simulations with the g_x and g_y as main outputs.






If someone can give-me an insight I would be very glad.