msdarvishi
Full Member level 4
Dear all,
I am using ISE 14.7 targeting a Virtex-5 FPGA. I wrote a VHDL code for the attached figure containing a clk50MHz module, an LFSR and a pulse counter.
The clk50MHz has an input clock of 100MHz and provides a 50MHz clock at its output to feed the LFSR.
The LFSR is used to generate random pattern as an input pulse for pulse counter module.
The pulse counter measures the period of its input signal (here is the 7th bit of count output in LFSR)
While I simulated each module individually in the hierarchy design, their corresponding testbench and the results are very nice and they work !
They problem is when I try to simulate the whole Top module that contains all three sub modules (clk50MHz, LFSR, and pulse counter). As you see in the attached timing diagram, the data_o output goes to UUUUUUUUUUUU state while the pulse counter works very nice. I tried to see the action of submodules in simulation of Top file and I see the LFSR receives the 50MHz clock as its input clock but it does not start counting !!!!
It is noticable that I have assigned the DATA_O signal to '0' state at the beginning of testbench but it does not work !!
I also attached the design files. Can anybody help me to solve this problem? My case is urgent and I do not know how to solve it ?!! Kind replies and helps are mostly appreciated.
Regards,
View attachment sources.rar
I am using ISE 14.7 targeting a Virtex-5 FPGA. I wrote a VHDL code for the attached figure containing a clk50MHz module, an LFSR and a pulse counter.
The clk50MHz has an input clock of 100MHz and provides a 50MHz clock at its output to feed the LFSR.
The LFSR is used to generate random pattern as an input pulse for pulse counter module.
The pulse counter measures the period of its input signal (here is the 7th bit of count output in LFSR)
While I simulated each module individually in the hierarchy design, their corresponding testbench and the results are very nice and they work !
They problem is when I try to simulate the whole Top module that contains all three sub modules (clk50MHz, LFSR, and pulse counter). As you see in the attached timing diagram, the data_o output goes to UUUUUUUUUUUU state while the pulse counter works very nice. I tried to see the action of submodules in simulation of Top file and I see the LFSR receives the 50MHz clock as its input clock but it does not start counting !!!!
It is noticable that I have assigned the DATA_O signal to '0' state at the beginning of testbench but it does not work !!
I also attached the design files. Can anybody help me to solve this problem? My case is urgent and I do not know how to solve it ?!! Kind replies and helps are mostly appreciated.
Regards,
View attachment sources.rar