simulation of complete system

[syedshan]

Hi all,

I have done simulating the submodules of my design and now I am integrating my design to the whole system. I am using 4DSP development board. It has PCIe communication to PC and also DDR3 for which I was working. We communicate through the board using c++ language.

They have some pre-built entities, for command generation, PCIe communication, and clock generation. so I will integrate my design...
Now the thing is I have no idea how to simulate my design in this scenario when I have to send the C++ commands, how can I emulate the C++ commands generation...then sending and receiving of DMA data...

looking for responses.

Bests,
Shan

 

[TrickyDicky]

you dont send c++ commands, C++ is a programming language to instruct your hardware to perform some tasks - so the commands will come in via some interface (what is the connection that these non-C++ instructions are sent)? Are you using PCIe?

Either way, for a simulation you will have to emulate these commands.

 

[syedshan]

Thanks,

Yes I am using PCIe and yes I know I have to emulate the c++ commands...But that is the isseu, how to do that?

Like should I just give some signals in VHDL and assume them to be C++ command's activating signal or what?
secondly I have to tx/rx data through DMA to/from PC, how to emulate that...coz simulating using the file saving or reading file does not, at all, emulate the actual PCIe DMA transfer...

waiting.

 

[TrickyDicky]

you will need a PCIe core in your FPGA, so this will have some form of interface. The PCIe core should be simulatable and will probably have a behavioural model, otherwise it probably wont be too hard to write a behavioural model of the PCIe core interface. Is it memory mapped or does it provide the PCIe TLPs? if its the second, you will need to read up on PCIe!

and also - stop reffering to C++ commands. The C++ is instructing the PC to send data via the PCIe bus. So what you get at the FPGA is PCIe packets (or it could just be an easy memory mapped interface). The commands will be defined by yourself, not the C++, otherwise how would you be able to understand them in the FPGA?

 

[syedshan]

thanks again

and also - stop reffering to C++ commands. The C++ is instructing the PC to send data via the PCIe bus. So what you get at the FPGA is PCIe packets (or it could just be an easy memory mapped interface). The commands will be defined by yourself, not the C++, otherwise how would you be able to understand them in the FPGA?

ok! now I understand this thing about commands, but as I have told below, 4DSP has provided with the static libraries with C++ commands and function for communicate and control with development board parameters, like ADC, DMA Tx, PLL, synthesizer etc.

The PCIe core should be simulatable and will probably have a behavioural model, otherwise it probably wont be too hard to write a behavioural model of the PCIe core interface. Is it memory mapped or does it provide the PCIe TLPs? if its the second, you will need to read up on PCIe!

As far as this point is concerned actually the 4DSP has provided the basic communication firmwares, like PCIe core is already deeloped by them and it is over virtex-5 FPGA while they have provided virtex-6 FPGA for implementing any DSP algorithm and further more provided communication firmwares as well b/w virtex-6 and virtex-5(PCIe FPGA, as you may say). So primarily I have not done PCIe at all during all this time and if you remember I have been asking about my image processing algo and DDR3 communication.

Well just for info, they had sample codes for DMA communication and few other programs, but they are complete programs with C++ interface and fully developed firwmware, so I dont even know how to simulate that thing to get started and have an idea.

Hope this helps to let you understand what I want to ask