simulation many voltage sources in Cadence

[songhe]

Dear all,

I need 4000 voltage sources in Cadence to simulate my circuit. Each voltage source will provide a pulse, and there is a 100ps time delay between each two pulses.

Anyone who has a better idea to realize theses? I do not want to copy 4000 times....

Best wishes,
Thanks in advance/

 

[Rohitchampion]

i guess you have no other option than copying.

 

[erikl]

Anyone who has a better idea to realize theses? I do not want to copy 4000 times....

Create a cell with a (functional) 100ps delay + a VCVS. Then instanciate this cell 3999 times: cellname[3999:1], this should give you 3999 output nodes out[3999:1]. Then stimulate it with a single VPULSE output out[0].

 

[songhe]

Create a cell with a (functional) 100ps delay + a VCVS. Then instanciate this cell 3999 times: cellname[3999:1], this should give you 3999 output nodes out[3999:1]. Then stimulate it with a single VPULSE output out[0].

Dear erikl
I got your idea.
And the simulation is very low, since there are 4000 delay lines.

Thank you very much.

 

[dick_freebird]

You might be better off with a veriloga source that reads
tabular data (or has it embedded in the code). I've built
these using a concatenation of header, "core" and tail
using shell scripts to massage plain text, time voltage
pairs at one per line, to make very long "digital" vectors.
Since the header and tail don't change the veriloga
"source" can easily be rebuilt - although you will still have
to null-edit and save the veriloga from within the design
system to get it refreshed properly.

 

[erikl]

I got your idea.
And the simulation is very low, since there are 4000 delay lines.

I forgot to mention - in order to chain the delayed pulse sources - you also have to create an assign array, by which you assign the output of the previous cell to the input of the following cell. Formerly I did this with a patchCord array - don't know if this element is still available.

But it should also work directly within the delay cell: if you create 3999 delay cells with the name (e.g.) delay[1:3999], you name the inputs out[1:3999] (3999 inputs, the 1^st one out[1] comes from the VPULSE source) and the outputs out[2:4000] (3999 outputs), together with out[1] you have 4000 outputs in total.

But I guess this necessity was already clear to you.

 

[songhe]

You might be better off with a veriloga source that reads
tabular data (or has it embedded in the code). I've built
these using a concatenation of header, "core" and tail
using shell scripts to massage plain text, time voltage
pairs at one per line, to make very long "digital" vectors.
Since the header and tail don't change the veriloga
"source" can easily be rebuilt - although you will still have
to null-edit and save the veriloga from within the design
system to get it refreshed properly.

Hi dick_freebird,

Thanks very much.