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Simulation for Static performance of the DAC/ADC

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snoop835

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Hi everyone.

I am currently designing R2R 8-bits DAC. Now I want to simulate the DAC static performance i.e. offset error, gain error, INL and DNL. What I did was, I generated an ideal 8-bit DAC and compared the transfer slope to the actual DAC (ideal DAC slope vs actual DAC slope). From this I can directly measure INL/DNL/Offset?Gain Error. However I'm not sure whether this is the correct way of doing it!

Can anybody consult me on this problem.

CHEERS.......................
 

i do in the same way as u did. for ideal DAC, u just need a mathematic model, there is no need to design it with ideal blocks
 

Thanks analogic1!

I managed to generate ideal DAC transfer slope using ideal DAC. Then I compare it with actual DAC transfer slope. From this I measured the INL/DNL/Offset/Gain error directly from the simulation (ideal slope vs actual slope). However I couldn't get the correct measurement result using this method.

Is the method I used is correct to characterise the DAC static performance? Is there any other method which is more reliable?

I read an article about measuring INL/DNL using transition point. Roughly in this method we need to measure the transition voltage from 11010 to 11011. Then we need to apply certain formulas to calculate for INL/DNL. Is this a valid way to characterise the DAC static performance?Anyone has good references on this method?

CHEERS........
 

Though I had well read your message that talks about DAC, here is a doc that explain how to test an ADC...

Let's assume that parameters are quite the same... nevertheless, I think that methods are similar

bye
 

Thank you manitooo, your post would be very helpful. :D
 

really thanks for the rar file for testing
 

thanks a lot
 

you could use Matlab deal with the data you get from simulation with spice。Or search some info from net.

Added after 3 minutes:

The file manitooo uploaded is so detail ,I think enough for you.
 

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