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simulation and synthesis in VHDL

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How to do simulation and synthesis in VHDL
 

Be more specific..
Answer to above question:Simulation-> Use modelsim..Synthesis-> Use ISE or VIVADO or DC Compiler...
 

How to do simulation and synthesis in VHDL

I believe the answer for your question is simple. You need to google it or see some videos where you have the convenience of copying and pasting the code in your compiler and then do the simulations.
 

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