Read Chapter9 of the docu mentioned in the above post.
1st and foremost, did you generate the core successfully?
If yes, just right_click inside Vivado on the core top_level file and generate its "example_design".
Vivado will create a new project for you with a test_bench wrapper over the core.
Then open this new project and just "Run Simulation".
Thanks very much for all your help. This was exactly what I needed
- - - Updated - - -
Hi Paul
thanks for your response. I am able to simulate it but not using the way you described and would be interested to replicate that... When I right click (.......xci) file I don't see the option of generating example design.... Please advise.
See Chapter8 of the IP core spec - "No example design is available at the time for the SMPTE SD/HD/3G-SDI 3.0 core"
So ignore the way of generation I mentioned above.
But see Chapter9: "A demonstration test bench is provided with the core which enables you to observe core behavior in a typical scenario. This test be nch is generated together with the core in Vivado Design Suite."
BTW Thanks for all your help. I was able to simulate in vivado. What do I need to do if I want to simulate in modelsim/questasim. thanks very much
- - - Updated - - -
The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the video formats. Also it is just running one record and I would appreciate your help as to figure out why and how to run all the records. Many thanks