simulating long strings in VHDL

procedure send_string(        str     : in  string;
                       signal clk     : in  std_logic;
                       signal op      : out std_logic
                      ) is  
  
  variable temp_ascii   : unsigned(7 downto 0);
begin
  
  for i in str'range loop
    
    temp_ascii := to_unsigned( character'pos( str(i) ), 8 );  --character type is positioned according to ascii codes
    
    for j in temp_ascii'range loop
      op <= temp_ascii(j);
      
      wait until rising_edge(clk);      
    end loop;
  end loop;
  
end procedure;

.....................

process
begin
  send_string( str => "This is a very long string but it will transmit each character bit by bit",
               clk => clk,
               op  => op
             );
  wait;
end process;