simulate the top level Vdd, Vss, gnd current in cadence?

cadence vdd!

in cadence I am building the top level circuits by several blocks, in other words, the top level block is consisted of several circuits blocks.

each block use the symbol Vdd, Vss, gnd from the analoglib. When I create a circuit symbol from the schematic, these Vdd, Vss, gnd are not taken as the Pins of the symbol, it seems like these signals are considered as global signals

Now I am running simulation on the top level schematic, and I want to know the total current consumption, therefore, i am interested to know the current flowing through Vdd, Vss and gnd.

But because there is no PIN for these global signals, so I can't find a way to display the total current consumption directly.

so I want to know how can I simulate these global signal currents? thanks

vdd_inherit

For whole circuit the current consumption u can see as current flowing thought voltage sources.
I give u some advice it's better to use an inherited connections rather than global. Very usefull thing. How to use this u can read in cadence documentation. This gives u an opportunity to change supply connections for specific instances and thier embedded instances.
In ur case, u can change supply net name e.g. "vdd!" for some "local_vdd" for block. Than place "presistor" instance from analogLib between "vdd!" and "local_vdd". So u can watch that current flow in block. Note: "presistor" isn't sent to layout, equally it's short.
See vdd_inherit and vss_inherit in analogLib.
I use inherited connection for separate power,analog, digital and esd supply's rails. I connect them together though presistors on the top level (usually i have one pin for vdd and one for gnd). So I can take some estimation of on-chip rail's resistance, use bound wire models. Also layouter isn't able to connect analog and digital supplies in designed block.