Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Simulate the output voltage transient, provided output impedance transfer function

Status
Not open for further replies.

hairizaman

Newbie level 1
Joined
Jan 8, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
8
Hi,

In general, how I can simulate the output voltage transient in time domain if I have the open loop output impedance transfer function?

In specific, I would like to simulate the output voltage transient in time domain for a LDO (low dropout) regulator.

I have the open loop output impedance transfer function based on a the paper by Everett Rogers, "Stability analysis of low-dropout linear regulators with a PMOS pass element", Analog Application Journal, Texas Instruments, 1999. The paper can be retrieved from www.ti.com/lit/an/slyt194/slyt194.pdf

Thank you.

Hairi
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top