Nightlamp,
I would assume that c_in is your carrier bit?....If so the beauty of VHDL is that VHDL takes care of the carrier bit for you. Are you trying to add from 000 to 111? If so you can use integer range instead of std_logic when you declare your variables. something like this
PORT(
A:IN INTEGER RANGE 0 to 7;
SUM:OUT INTEGER RANGE 0 to 7);
Then in your architecture you can just use SUM <= A+1; this will give you all the values between 000 and 111.
Hope this was what you are talking about.
Are you trying to add A and B, or just make an adder that starts at 000 and ends at 111?