Simple VHDL design- carry flag defign

[laiza]

Simple VHDL design

Hi can anyone help me with this? How can I have a code that would compare the result of 2 (16Bits) added together? I mean if I add 16 bits to another 16bits the answer should be 16 bits and if it is over 16 like 17 then it will give me "1".How am i supposed to do that on VHDL? Appreciate your brilliant logical ideas....

 

[ckaa]

Re: Simple VHDL design

I do not know the exact VHDL syntax but I could list out the steps involved:
1. declare a 17-bit vector 'sum' and a single bit variable 'flag'.
2. Your input would be you two 16-bit numbers, lets say 'A' and 'B'.
3. After this declaration assign 'sum = A +B'.
4. Use an if statement to check your 17th bit of your variable 'sum'.
5. If sum[17] == 1 , then assert 'flag = 1' else 'flag=0'.
I hope this answers your question.