srinpraveen
Member level 2
I have a logic that happens at every rising clock edge. I want to do a simple action. I will tell you the situation.
signal a should be 0 as long as signal b is 1. How do i implement this in verilog code other than the conventional if else happening at always @(posedge clk or negedge rst_n) to check this ??
Is there some verilog construct (I mean synthesizable verilog construct) like signal a=0 until signal b=1 ??
signal a should be 0 as long as signal b is 1. How do i implement this in verilog code other than the conventional if else happening at always @(posedge clk or negedge rst_n) to check this ??
Is there some verilog construct (I mean synthesizable verilog construct) like signal a=0 until signal b=1 ??